Incorrect output with weston-simple-dmabuf-feedback run with Mesa's Zink driver
Affected version
- Fedora 38
- Mutter main
- Wayland
Bug summary
Running weston-simple-dmabuf-feedback
with MESA_LOADER_DRIVER_OVERRIDE=zink
in a GNOME Shell session produces incorrect output. This is a contrast to behaviour under Weston, where weston-simple-dmabuf-feedback
renders correctly under the same circumstances.
Output differs visually depending on whether MUTTER_DEBUG_SEND_KMS_MODIFIERS=1
is set.
Steps to reproduce
- Ensure Weston demos are installed and that you have a build of Mesa with Zink enabled
- Launch the
weston-simple-dmabuf-feedback
demo with the environment variableMESA_LOADER_DRIVER_OVERRIDE=zink
-
weston-simple-dmabuf-feedback
should appear visually garbled (presumably only with direct scanout).
What did you expect to happen
Under Weston, the output of this is correct and not visually garbled. I expected this to be the case under GNOME Shell/Mutter as well.
Relevant logs, screenshots, screencasts etc.
The logged output of weston-simple-dmabuf-feedback
with Zink under Mutter (with MUTTER_DEBUG_SEND_KMS_MODIFIERS=1
):
bt@mako ~ % MESA_LOADER_DRIVER_OVERRIDE=zink weston-simple-dmabuf-feedback
This client was written with the purpose of manually test Weston's dma-buf feedback implementation. See main() description for more details on how to test this.
feedback: main device /dev/dri/renderD128
├─── tranche: target device /dev/dri/renderD128, no flags
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ARGB8888, modifier LINEAR (0x0)
│ ├─── format ARGB8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR8888, modifier LINEAR (0x0)
│ ├─── format ABGR8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XRGB8888, modifier LINEAR (0x0)
│ ├─── format XRGB8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR8888, modifier LINEAR (0x0)
│ ├─── format XBGR8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ARGB2101010, modifier LINEAR (0x0)
│ ├─── format ARGB2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR2101010, modifier LINEAR (0x0)
│ ├─── format ABGR2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XRGB2101010, modifier LINEAR (0x0)
│ ├─── format XRGB2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR2101010, modifier LINEAR (0x0)
│ ├─── format XBGR2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format RGB565, modifier LINEAR (0x0)
│ ├─── format RGB565, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR16161616F, modifier LINEAR (0x0)
│ ├─── format ABGR16161616F, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR16161616F, modifier LINEAR (0x0)
│ ├─── format XBGR16161616F, modifier NONE_INVALID (0xffffffffffffff)
│ └─── end of tranche
└─── end of dma-buf feedback
feedback: main device /dev/dri/renderD128
├─── tranche: target device /dev/dri/card1, scanout
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ARGB8888, modifier LINEAR (0x0)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR8888, modifier LINEAR (0x0)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XRGB8888, modifier LINEAR (0x0)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR8888, modifier LINEAR (0x0)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ARGB2101010, modifier LINEAR (0x0)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR2101010, modifier LINEAR (0x0)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XRGB2101010, modifier LINEAR (0x0)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR2101010, modifier LINEAR (0x0)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format RGB565, modifier LINEAR (0x0)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR16161616F, modifier LINEAR (0x0)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR16161616F, modifier LINEAR (0x0)
│ └─── end of tranche
├─── tranche: target device /dev/dri/renderD128, no flags
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ARGB8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ARGB8888, modifier LINEAR (0x0)
│ ├─── format ARGB8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR8888, modifier LINEAR (0x0)
│ ├─── format ABGR8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XRGB8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XRGB8888, modifier LINEAR (0x0)
│ ├─── format XRGB8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR8888, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR8888, modifier LINEAR (0x0)
│ ├─── format XBGR8888, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ARGB2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ARGB2101010, modifier LINEAR (0x0)
│ ├─── format ARGB2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR2101010, modifier LINEAR (0x0)
│ ├─── format ABGR2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XRGB2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XRGB2101010, modifier LINEAR (0x0)
│ ├─── format XRGB2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_RETILE,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x200000440517901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR2101010, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR2101010, modifier LINEAR (0x0)
│ ├─── format XBGR2101010, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format RGB565, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format RGB565, modifier LINEAR (0x0)
│ ├─── format RGB565, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format ABGR16161616F, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format ABGR16161616F, modifier LINEAR (0x0)
│ ├─── format ABGR16161616F, modifier NONE_INVALID (0xffffffffffffff)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051ba01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,DCC,DCC_PIPE_ALIGN,DCC_INDEPENDENT_64B,DCC_MAX_COMPRESSED_BLOCK=64B,DCC_CONSTANT_ENCODE,PIPE_XOR_BITS=2,BANK_XOR_BITS=0,RB=1,PIPE_2 (0x20000044051b901)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401a01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S_X,PIPE_XOR_BITS=2,BANK_XOR_BITS=0 (0x200000000401901)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_D (0x200000000000a01)
│ ├─── format XBGR16161616F, modifier AMD_GFX9,GFX9_64K_S (0x200000000000901)
│ ├─── format XBGR16161616F, modifier LINEAR (0x0)
│ ├─── format XBGR16161616F, modifier NONE_INVALID (0xffffffffffffff)
│ └─── end of tranche
└─── end of dma-buf feedback
System information:
System:
Host: mako Kernel: 6.2.8-300.fc38.x86_64 arch: x86_64 bits: 64 compiler: gcc
v: 2.39-9.fc38 Desktop: GNOME v: 44.0 tk: GTK v: 3.24.37 wm: gnome-shell
dm: GDM Distro: Fedora release 38 (Thirty Eight)
CPU:
Info: 8-core model: AMD Ryzen 7 5800H with Radeon Graphics bits: 64
type: MT MCP arch: Zen 3 rev: 0 cache: L1: 512 KiB L2: 4 MiB L3: 16 MiB
Speed (MHz): avg: 2669 high: 3200 min/max: 1200/4462 boost: enabled cores:
1: 2535 2: 1963 3: 3200 4: 3200 5: 3200 6: 1985 7: 2160 8: 1915 9: 3200
10: 3200 11: 1439 12: 3200 13: 1916 14: 3200 15: 3200 16: 3200
bogomips: 102206
Flags: avx avx2 ht lm nx pae sse sse2 sse3 sse4_1 sse4_2 sse4a ssse3 svm
Graphics:
Device-1: AMD Cezanne [Radeon Vega Series / Radeon Mobile Series]
vendor: Lenovo driver: amdgpu v: kernel arch: GCN-5 pcie: speed: 8 GT/s
lanes: 16 ports: active: eDP-1 empty: DP-1,HDMI-A-1 bus-ID: 05:00.0
chip-ID: 1002:1638 temp: 46.0 C
Device-2: IMC Networks Integrated Camera type: USB driver: uvcvideo
bus-ID: 3-4:3 chip-ID: 13d3:56fb
Display: wayland server: X.org v: 1.20.14 with: Xwayland v: 23.1.1
compositor: gnome-shell driver: N/A display-ID: 0
Monitor-1: eDP-1 res: 2560x1600 size: N/A
API: OpenGL v: 4.6 Mesa 23.1.0-devel renderer: AMD Radeon Graphics
(renoir LLVM 15.0.7 DRM 3.49 6.2.8-300.fc38.x86_64) direct-render: Yes
Edited by Brendan William