diff --git a/.gitignore b/.gitignore
index 297975910a34c8cd1236ad1a397cc37ea473c815..6fddaab8ec100c8b19fcebc6f44bbda1f0064c06 100755
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,5 @@
 build/*
+.Xil/*
 artifacts/*
 hls/dma_lb_axis_switch/dma_lb_axis_switch/*
 log_data/*
diff --git a/hdl/s15611_driver.sv b/hdl/s15611_driver.sv
index 823d9eb07e24c22bb66d41af6d37556124157485..425cd4f55d71c3b3b5eb3d0392a5008f891b2987 100644
--- a/hdl/s15611_driver.sv
+++ b/hdl/s15611_driver.sv
@@ -20,18 +20,19 @@
 
 module s15611_driver
   #(
-     parameter NUMBER_OF_PIXEL = 128,
-     parameter SI_WIDTH_NCLK = 4,
-     parameter SENSOR_CLK_WIDTH_NCLK = 100,
-     parameter INITIAL_DELAY_NCLK = 18*SENSOR_CLK_WIDTH_NCLK,
-     parameter TS_NCLK = 35
+     parameter MASTER_CLK_MHZ = 100,
+     parameter MCLK_MHZ = 40,
+     parameter NUMBER_OF_PIXEL = 1024,
+     parameter MASTER_START_PULSE_PERIOD = 1162,
+     parameter MASTER_START_PULSE_HIGH_PERIOD = 167,
+     parameter CDC_REG_LENGTH = 4
    )
    (
      input master_clock,
      input resetn,
-	 // sensor interface
+     // sensor interface
      output s15611_mclk,
-     output s15611_mst,
+     output logic s15611_mst,
      output s15611_cs,
      input s15611_miso,
      output s15611_mosi,
@@ -40,52 +41,129 @@ module s15611_driver
      input s15611_sync,
      input s15611_pclk,
      input [11:0] s15611_data,
-	 // output data
-     output [11:0] data_out,
-     output [9:0] data_index,
-     output data_valid
+     // output data
+     output logic [11:0] data_out,
+     output logic [9:0] data_index,
+     output logic data_valid,
+     // debug port
+     output logic [3:0] dbg_state,
+     output logic [11:0] dbg_sensor_raw_data,
+     output logic [11:0] dbg_sensor_data,
+     output logic [9:0] dbg_sensor_index,
+     output logic dbg_sensor_valid
    );
 
-  reg [7:0] clk_counter;
-  reg [15:0] pixel_counter;
-  reg [31:0] si_counter;
-  reg initial_interval;
+  genvar i;
+  logic sensor_clock;
+  logic [15:0] mclk_counter;
+  logic data_capture_triger;
+  logic [15:0] pixel_counter;
+  enum logic [3:0] {BLANKING_PERIOD, SYNC_CLK1, SYNC_CLK2, CAPTURE_DATA} state;
+  (* ASYNC_REG="true" *)
+  logic [11:0] data_in_temp[CDC_REG_LENGTH:0];
+  (* ASYNC_REG="true" *)
+  logic [11:0] data_out_temp[CDC_REG_LENGTH:0];
+  (* ASYNC_REG="true" *)
+  logic [9:0] data_index_temp[CDC_REG_LENGTH:0];
+  (* ASYNC_REG="true" *)
+  logic data_valid_temp[CDC_REG_LENGTH:0];
+  // TODO: implement spi controller interface
+  assign s15611_cs = 1;
+  assign s15611_mosi = 0;
+  assign s15611_sclk = 0;
+  assign s15611_rstb = 0;
 
+  // drive sensor
+  assign s15611_mclk = master_clock;
   always_ff @(posedge master_clock)
   begin
-    if(clk_counter >= SENSOR_CLK_WIDTH_NCLK-1)
+    if(mclk_counter >= MASTER_START_PULSE_PERIOD-1)
     begin
-      cjmcu1401_clk = ~cjmcu1401_clk;
-      clk_counter <= 8'd0;
+      mclk_counter <= 0;
     end
     else
     begin
-      clk_counter = clk_counter +1;
-      if((clk_counter == TS_NCLK) && (initial_interval == 0))
-      begin
-        sample_capture_trigger <= 1'b1;
-        pixel_counter = pixel_counter + 1;
-      end
-      else
-      begin
-        sample_capture_trigger <= 1'b0;
-      end
+      mclk_counter <= mclk_counter + 1;
     end
-    if((32'd6 <= si_counter) && (si_counter <= (32'd6 + SI_WIDTH_NCLK)))
+
+    if (mclk_counter <=  MASTER_START_PULSE_HIGH_PERIOD-1)
     begin
-      si_counter = si_counter + 1;
-      cjmcu1401_si = 1'b1;
-      initial_interval = 1'b1;
+      s15611_mst <= 1;
     end
-    else if(si_counter >= INITIAL_DELAY_NCLK + NUMBER_OF_PIXEL * SENSOR_CLK_WIDTH_NCLK)
-      si_counter <= 32'd0;
     else
     begin
-      cjmcu1401_si = 1'b0;
-      si_counter = si_counter + 1;
+      s15611_mst <= 0;
     end
-    if(si_counter >= INITIAL_DELAY_NCLK )
-      initial_interval = 1'b0;
   end
-  assign pixel_counter_out = pixel_counter;
+
+  // capture data
+  always_ff @(posedge s15611_pclk)
+  begin
+    dbg_state <= state;
+    data_in_temp[0] <= s15611_data;
+    data_out_temp[0] <= 0;
+    data_valid_temp[0] <= 0;
+    case (state)
+      BLANKING_PERIOD :
+      begin
+        if (s15611_sync)
+        begin
+          state <= BLANKING_PERIOD;
+        end
+        else
+        begin
+          state <= SYNC_CLK1;
+        end
+      end
+      SYNC_CLK1 :
+      begin
+        state <= SYNC_CLK2;
+      end
+      SYNC_CLK2 :
+      begin
+        state <= CAPTURE_DATA;
+        data_out_temp[0] <= s15611_data;
+      end
+      CAPTURE_DATA :
+      begin
+        if (pixel_counter <= NUMBER_OF_PIXEL-1)
+        begin
+          state <= CAPTURE_DATA;
+          pixel_counter <= pixel_counter + 1;
+          data_out_temp[0] <= s15611_data;
+          data_index_temp[0] <= pixel_counter + 1;
+          data_valid_temp[0] <= 1;
+        end
+        else
+        begin
+          pixel_counter <= 0;
+          state <= BLANKING_PERIOD;
+        end
+      end
+    endcase
+  end
+
+  // CDC data
+  generate
+    for (i = 0; i < CDC_REG_LENGTH; i++)
+    begin: cdc_reg_delay
+      always_ff @(posedge master_clock)
+      begin
+        data_in_temp[i+1] <= data_in_temp[i];
+        data_out_temp[i+1] <= data_out_temp[i];
+        data_index_temp[i+1] <= data_index_temp[i];
+        data_valid_temp[i+1] <= data_valid_temp[i];
+      end
+    end
+  endgenerate
+
+  assign data_out = data_out_temp[CDC_REG_LENGTH];
+  assign data_index = data_index_temp[CDC_REG_LENGTH];
+  assign data_valid = data_valid_temp[CDC_REG_LENGTH];
+
+  assign dbg_sensor_raw_data = data_in_temp[CDC_REG_LENGTH];
+  assign dbg_sensor_data = data_out_temp[CDC_REG_LENGTH];
+  assign dbg_sensor_index = data_index_temp[CDC_REG_LENGTH];
+  assign dbg_sensor_valid = data_valid_temp[CDC_REG_LENGTH];
+
 endmodule
diff --git a/hdl/sensor_data_acquisition.v b/hdl/sensor_data_acquisition.v
index f150649f0c254ab6e3c18824a630d223c53b878d..58abe2bafbb042b7805a0e86301f48f2005d5689 100644
--- a/hdl/sensor_data_acquisition.v
+++ b/hdl/sensor_data_acquisition.v
@@ -19,75 +19,160 @@
 
 
 module sensor_data_acquisition
-  #(
-     parameter NUMBER_OF_PIXEL = 128,
-     parameter SI_WIDTH_NCLK = 4,
-     parameter SENSOR_CLK_WIDTH_NCLK = 100,
-     parameter INITIAL_DELAY_NCLK = 18*SENSOR_CLK_WIDTH_NCLK,
-     parameter TS_NCLK = 35
-   )
-   (
-     input master_clock,
-     input resetn,
-     // sensor interface
-     output s15611_mclk,
-     output s15611_mst,
-     output s15611_cs,
-     input s15611_miso,
-     output s15611_mosi,
-     output s15611_sclk,
-     output s15611_rstb,
-     input s15611_sync,
-     input s15611_pclk,
-     input [11:0] s15611_data,
-     // axis_data
-     input data_tready,
-     output [31:0] data_tdata,
-     output data_tlast,
-     output data_tvalid,
-     output data_tuser
-   );
+  (
+    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME master_clock, FREQ_HZ 40000000" *)
+    input master_clock,
+    input resetn,
+    // sensor interface
+    output s15611_mclk,
+    output s15611_mst,
+    output s15611_cs,
+    input s15611_miso,
+    output s15611_mosi,
+    output s15611_sclk,
+    output s15611_rstb,
+    input s15611_sync,
+    input s15611_pclk,
+    input [11:0] s15611_data,
+    // axis_data
+    (* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF data,  FREQ_HZ 40000000" *)
+    input data_tready,
+    output reg [31:0] data_tdata,
+    output reg data_tlast,
+    output reg data_tvalid,
+    // debug port
+    output reg [3:0] dbg_axis_state,
+    output [3:0] dbg_sensor_state,
+    output [11:0] dbg_sensor_raw_data,
+    output [11:0] dbg_sensor_data,
+    output [9:0] dbg_sensor_index,
+    output dbg_sensor_valid
+  );
 
-  reg [7:0] clk_counter;
-  reg [15:0] pixel_counter;
-  reg [31:0] si_counter;
-  reg initial_interval;
+  genvar i;
+  wire [11:0] sensor_data;
+  wire [9:0] sensor_data_index;
+  wire  sensor_data_valid;
+  reg [11:0] sensor_data_reg[5:0];
+  reg [9:0] sensor_data_index_reg[5:0];
+  reg sensor_data_valid_reg[5:0];
+  reg [31:0] time_counter;
+  localparam [31:0] HEADER_VALUE = 32'hAAAAAAAA;
+  localparam [31:0] FOOTER_VALUE = 32'h55555555;
+  localparam [3:0]  IDLE = 0, HEADER = 1, TIME_STAMP = 2, DATA = 3, FOOTER = 4;
+  reg [3:0] axis_state = IDLE;
+
+  s15611_driver s15611_driver_inst
+                (
+                  .master_clock(master_clock),
+                  .resetn(resetn),
+                  // sensor interface
+                  .s15611_mclk(s15611_mclk),
+                  .s15611_mst(s15611_mst),
+                  .s15611_cs(s15611_cs),
+                  .s15611_miso(s15611_miso),
+                  .s15611_mosi(s15611_mosi),
+                  .s15611_sclk(s15611_sclk),
+                  .s15611_rstb(s15611_rstb),
+                  .s15611_sync(s15611_sync),
+                  .s15611_pclk(s15611_pclk),
+                  .s15611_data(s15611_data),
+                  // output data
+                  .data_out(sensor_data),
+                  .data_index(sensor_data_index),
+                  .data_valid(sensor_data_valid),
+                  // debug port
+                  .dbg_state(dbg_sensor_state),
+				  .dbg_sensor_raw_data(dbg_sensor_raw_data),
+                  .dbg_sensor_data(dbg_sensor_data),
+				  .dbg_sensor_index(dbg_sensor_index),
+                  .dbg_sensor_valid(dbg_sensor_valid)
+                );
 
   always @(posedge master_clock)
   begin
-    if(clk_counter >= SENSOR_CLK_WIDTH_NCLK-1)
+    if (resetn)
     begin
-      cjmcu1401_clk = ~cjmcu1401_clk;
-      clk_counter <= 8'd0;
+      time_counter <= time_counter + 1;
+      sensor_data_reg[0] <= sensor_data;
+      sensor_data_index_reg[0] <= sensor_data_index;
+      sensor_data_valid_reg[0] <= sensor_data_valid;
     end
     else
     begin
-      clk_counter = clk_counter +1;
-      if((clk_counter == TS_NCLK) && (initial_interval == 0))
+      time_counter <= 0;
+    end
+  end
+
+  generate
+    for (i = 0; i < 5; i = i+1)
+    begin: shift_reg
+      always @(posedge master_clock)
       begin
-        sample_capture_trigger <= 1'b1;
-        pixel_counter = pixel_counter + 1;
+        sensor_data_reg[i+1] <= sensor_data_reg[i];
+        sensor_data_index_reg[i+1] <= sensor_data_index_reg[i];
+        sensor_data_valid_reg[i+1] <= sensor_data_valid_reg[i];
       end
-      else
+    end
+  endgenerate
+
+  // prepare data packet
+  always @(posedge master_clock)
+  begin
+    dbg_axis_state <= axis_state;
+    data_tdata <= 0;
+    data_tvalid <= 0;
+    data_tlast <= 0;
+    case (axis_state)
+      IDLE:
       begin
-        sample_capture_trigger <= 1'b0;
+        if ((sensor_data_valid == 1) && (sensor_data_valid_reg[0] == 0))
+        begin
+          axis_state <= HEADER;
+        end
+        else
+        begin
+          axis_state <= IDLE;
+        end
       end
-    end
-    if((32'd6 <= si_counter) && (si_counter <= (32'd6 + SI_WIDTH_NCLK)))
-    begin
-      si_counter = si_counter + 1;
-      cjmcu1401_si = 1'b1;
-      initial_interval = 1'b1;
-    end
-    else if(si_counter >= INITIAL_DELAY_NCLK + NUMBER_OF_PIXEL * SENSOR_CLK_WIDTH_NCLK)
-      si_counter <= 32'd0;
-    else
-    begin
-      cjmcu1401_si = 1'b0;
-      si_counter = si_counter + 1;
-    end
-    if(si_counter >= INITIAL_DELAY_NCLK )
-      initial_interval = 1'b0;
+
+      HEADER:
+      begin
+        data_tdata <= HEADER_VALUE;
+        data_tvalid <= 1;
+        axis_state <= TIME_STAMP;
+      end
+
+      TIME_STAMP:
+      begin
+        data_tdata <= time_counter;
+        data_tvalid <= 1;
+        axis_state <= DATA;
+      end
+
+      DATA:
+      begin
+        if (sensor_data_index_reg[3] < 1023)
+        begin
+          axis_state <= DATA;
+          data_tdata <= {10'd0, sensor_data_index_reg[3], sensor_data_reg[3]};
+          data_tvalid <= 1;
+        end
+        else if (sensor_data_index_reg[3] == 1023)
+        begin
+          axis_state <= FOOTER;
+          data_tdata <= {10'd0, sensor_data_index_reg[3], sensor_data_reg[3]};
+          data_tvalid <= 1;
+        end
+      end
+
+      FOOTER:
+      begin
+        data_tdata <= FOOTER_VALUE;
+        data_tvalid <= 1;
+        data_tlast <= 1;
+        axis_state <= IDLE;
+      end
+    endcase
   end
-  assign pixel_counter_out = pixel_counter;
 endmodule
diff --git a/tcl/create_vivado_project.tcl b/tcl/create_vivado_project.tcl
index 88f78bd3d0e1c8b722ef89c5ababca447e90d916..217ff3666a929f759c329f8972b9fee84da600c2 100644
--- a/tcl/create_vivado_project.tcl
+++ b/tcl/create_vivado_project.tcl
@@ -18,7 +18,7 @@
 #
 # create_vivado_project.tcl: Tcl script for re-creating project 'vivado'
 #
-# Generated by Vivado on Wed Apr 13 17:33:26 +0430 2022
+# Generated by Vivado on Sun Apr 17 09:13:55 +0430 2022
 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -42,9 +42,9 @@
 #
 # 3. The following remote source files that were added to the original project:-
 #
-#    "/home/beheshti/projects/fz3/hdl/sensor_data_acquisition.v"
-#    "/home/beheshti/projects/fz3/hdl/s15611_driver.sv"
-#    "/home/beheshti/projects/fz3/xdc/top.xdc"
+#    "/home/beheshti/FZ3/hdl/s15611_driver.sv"
+#    "/home/beheshti/FZ3/hdl/sensor_data_acquisition.v"
+#    "/home/beheshti/FZ3/xdc/top.xdc"
 #
 #*****************************************************************************************
 
@@ -57,8 +57,8 @@ set origin_dir [file dirname [file dirname [info script]]]
 proc checkRequiredFiles { origin_dir} {
   set status true
   set files [list \
- "[file normalize "$origin_dir/hdl/sensor_data_acquisition.v"]"\
  "[file normalize "$origin_dir/hdl/s15611_driver.sv"]"\
+ "[file normalize "$origin_dir/hdl/sensor_data_acquisition.v"]"\
  "[file normalize "$origin_dir/xdc/top.xdc"]"\
   ]
   foreach ifile $files {
@@ -183,7 +183,7 @@ set_property -name "webtalk.questa_export_sim" -value "1" -objects $obj
 set_property -name "webtalk.riviera_export_sim" -value "1" -objects $obj
 set_property -name "webtalk.vcs_export_sim" -value "1" -objects $obj
 set_property -name "webtalk.xsim_export_sim" -value "1" -objects $obj
-set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
 if {[string equal [get_filesets -quiet sources_1] ""]} {
@@ -202,8 +202,8 @@ if { $obj != {} } {
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
 set files [list \
- [file normalize "${origin_dir}/hdl/sensor_data_acquisition.v"] \
  [file normalize "${origin_dir}/hdl/s15611_driver.sv"] \
+ [file normalize "${origin_dir}/hdl/sensor_data_acquisition.v"] \
 ]
 add_files -norecurse -fileset $obj $files
 
@@ -256,6 +256,7 @@ set obj [get_filesets sim_1]
 # Set 'sim_1' fileset properties
 set obj [get_filesets sim_1]
 set_property -name "top" -value "design_1_wrapper" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
 set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
 
 # Set 'utils_1' fileset object
@@ -291,6 +292,7 @@ proc cr_bd_design_1 { parentCell } {
   set bCheckIPs 1
   if { $bCheckIPs == 1 } {
      set list_check_ips "\ 
+  xilinx.com:ip:clk_wiz:6.0\
   xilinx.com:ip:axi_clock_converter:2.1\
   xilinx.com:ip:axi_dma:7.1\
   NoiseIran:hls:dma_lb_axis_switch:1.0\
@@ -390,8 +392,9 @@ proc create_hier_cell_sensor_ss { parentCell nameHier } {
 
 
   # Create pins
-  create_bd_pin -dir I -type clk master_clock
-  create_bd_pin -dir I -type rst resetn
+  create_bd_pin -dir I -type clk clk_300mhz
+  create_bd_pin -dir I -type clk clk_40mhz
+  create_bd_pin -dir I -type rst clk_40mhz_resetn
   create_bd_pin -dir O s15611_cs
   create_bd_pin -dir I -from 11 -to 0 s15611_data
   create_bd_pin -dir O s15611_mclk
@@ -403,6 +406,12 @@ proc create_hier_cell_sensor_ss { parentCell nameHier } {
   create_bd_pin -dir O s15611_sclk
   create_bd_pin -dir I s15611_sync
 
+  # Create instance: axis_data_fifo_0, and set properties
+  set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+  set_property -dict [ list \
+   CONFIG.IS_ACLK_ASYNC {1} \
+ ] $axis_data_fifo_0
+
   # Create instance: sensor_data_acquisition_0, and set properties
   set block_name sensor_data_acquisition
   set block_cell_name sensor_data_acquisition_0
@@ -414,12 +423,40 @@ proc create_hier_cell_sensor_ss { parentCell nameHier } {
      return 1
    }
   
+  # Create instance: sensor_ila, and set properties
+  set sensor_ila [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 sensor_ila ]
+  set_property -dict [ list \
+   CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
+   CONFIG.C_DATA_DEPTH {4096} \
+   CONFIG.C_EN_STRG_QUAL {1} \
+   CONFIG.C_INPUT_PIPE_STAGES {3} \
+   CONFIG.C_MON_TYPE {MIX} \
+   CONFIG.C_NUM_OF_PROBES {6} \
+   CONFIG.C_PROBE0_MU_CNT {2} \
+   CONFIG.C_PROBE1_MU_CNT {2} \
+   CONFIG.C_PROBE2_MU_CNT {2} \
+   CONFIG.C_PROBE3_MU_CNT {2} \
+   CONFIG.C_PROBE4_MU_CNT {2} \
+   CONFIG.C_PROBE5_MU_CNT {2} \
+   CONFIG.C_PROBE6_MU_CNT {2} \
+   CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \
+ ] $sensor_ila
+
   # Create interface connections
-  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins data] [get_bd_intf_pins sensor_data_acquisition_0/data]
+  connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins data] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+  connect_bd_intf_net -intf_net sensor_data_acquisition_data [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins sensor_data_acquisition_0/data]
+  connect_bd_intf_net -intf_net [get_bd_intf_nets sensor_data_acquisition_data] [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins sensor_ila/SLOT_0_AXIS]
 
   # Create port connections
-  connect_bd_net -net S00_ARESETN_1 [get_bd_pins resetn] [get_bd_pins sensor_data_acquisition_0/resetn]
-  connect_bd_net -net pl_clk3 [get_bd_pins master_clock] [get_bd_pins sensor_data_acquisition_0/master_clock]
+  connect_bd_net -net S00_ARESETN_1 [get_bd_pins clk_40mhz_resetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins sensor_data_acquisition_0/resetn] [get_bd_pins sensor_ila/resetn]
+  connect_bd_net -net dbg_axis_state [get_bd_pins sensor_data_acquisition_0/dbg_axis_state] [get_bd_pins sensor_ila/probe0]
+  connect_bd_net -net dbg_sensor_data [get_bd_pins sensor_data_acquisition_0/dbg_sensor_data] [get_bd_pins sensor_ila/probe3]
+  connect_bd_net -net dbg_sensor_index [get_bd_pins sensor_data_acquisition_0/dbg_sensor_index] [get_bd_pins sensor_ila/probe4]
+  connect_bd_net -net dbg_sensor_raw_data [get_bd_pins sensor_data_acquisition_0/dbg_sensor_raw_data] [get_bd_pins sensor_ila/probe2]
+  connect_bd_net -net dbg_sensor_state [get_bd_pins sensor_data_acquisition_0/dbg_sensor_state] [get_bd_pins sensor_ila/probe1]
+  connect_bd_net -net dbg_sensor_valid [get_bd_pins sensor_data_acquisition_0/dbg_sensor_valid] [get_bd_pins sensor_ila/probe5]
+  connect_bd_net -net m_axis_aclk_0_1 [get_bd_pins clk_300mhz] [get_bd_pins axis_data_fifo_0/m_axis_aclk]
+  connect_bd_net -net pl_clk3 [get_bd_pins clk_40mhz] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins sensor_data_acquisition_0/master_clock] [get_bd_pins sensor_ila/clk]
   connect_bd_net -net s15611_data_0_1 [get_bd_pins s15611_data] [get_bd_pins sensor_data_acquisition_0/s15611_data]
   connect_bd_net -net s15611_miso_0_1 [get_bd_pins s15611_miso] [get_bd_pins sensor_data_acquisition_0/s15611_miso]
   connect_bd_net -net s15611_pclk_0_1 [get_bd_pins s15611_pclk] [get_bd_pins sensor_data_acquisition_0/s15611_pclk]
@@ -431,6 +468,57 @@ proc create_hier_cell_sensor_ss { parentCell nameHier } {
   connect_bd_net -net sensor_data_acquisit_0_s15611_rstb [get_bd_pins s15611_rstb] [get_bd_pins sensor_data_acquisition_0/s15611_rstb]
   connect_bd_net -net sensor_data_acquisit_0_s15611_sclk [get_bd_pins s15611_sclk] [get_bd_pins sensor_data_acquisition_0/s15611_sclk]
 
+  # Perform GUI Layout
+  regenerate_bd_layout -hierarchy [get_bd_cells /sensor_ss] -layout_string {
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.803509",
+   "Default View_TopLeft":"-319,0",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port data -pg 1 -lvl 3 -x 800 -y 90 -defaultsOSRD
+preplace port port-id_clk_300mhz -pg 1 -lvl 0 -x 0 -y 120 -defaultsOSRD
+preplace port port-id_clk_40mhz -pg 1 -lvl 0 -x 0 -y 140 -defaultsOSRD
+preplace port port-id_clk_40mhz_resetn -pg 1 -lvl 0 -x 0 -y 160 -defaultsOSRD
+preplace port port-id_s15611_cs -pg 1 -lvl 3 -x 800 -y 240 -defaultsOSRD
+preplace port port-id_s15611_mclk -pg 1 -lvl 3 -x 800 -y 200 -defaultsOSRD
+preplace port port-id_s15611_miso -pg 1 -lvl 0 -x 0 -y 290 -defaultsOSRD
+preplace port port-id_s15611_mosi -pg 1 -lvl 3 -x 800 -y 260 -defaultsOSRD
+preplace port port-id_s15611_mst -pg 1 -lvl 3 -x 800 -y 220 -defaultsOSRD
+preplace port port-id_s15611_pclk -pg 1 -lvl 0 -x 0 -y 330 -defaultsOSRD
+preplace port port-id_s15611_rstb -pg 1 -lvl 3 -x 800 -y 550 -defaultsOSRD
+preplace port port-id_s15611_sclk -pg 1 -lvl 3 -x 800 -y 280 -defaultsOSRD
+preplace port port-id_s15611_sync -pg 1 -lvl 0 -x 0 -y 310 -defaultsOSRD
+preplace portBus s15611_data -pg 1 -lvl 0 -x 0 -y 350 -defaultsOSRD
+preplace inst axis_data_fifo_0 -pg 1 -lvl 2 -x 660 -y 90 -defaultsOSRD
+preplace inst sensor_ila -pg 1 -lvl 2 -x 660 -y 410 -defaultsOSRD
+preplace inst sensor_data_acquisition_0 -pg 1 -lvl 1 -x 240 -y 300 -defaultsOSRD
+preplace netloc S00_ARESETN_1 1 0 2 20 100 510
+preplace netloc dbg_axis_state 1 1 1 520 320n
+preplace netloc dbg_sensor_state 1 1 1 500 340n
+preplace netloc m_axis_aclk_0_1 1 0 2 NJ 120 NJ
+preplace netloc pl_clk3 1 0 2 30 110 540
+preplace netloc s15611_data_0_1 1 0 1 NJ 350
+preplace netloc s15611_miso_0_1 1 0 1 NJ 290
+preplace netloc s15611_pclk_0_1 1 0 1 NJ 330
+preplace netloc s15611_sync_0_1 1 0 1 NJ 310
+preplace netloc sensor_data_acquisit_0_s15611_cs 1 1 2 NJ 240 NJ
+preplace netloc sensor_data_acquisit_0_s15611_mclk 1 1 2 NJ 200 NJ
+preplace netloc sensor_data_acquisit_0_s15611_mosi 1 1 2 NJ 260 NJ
+preplace netloc sensor_data_acquisit_0_s15611_mst 1 1 2 NJ 220 NJ
+preplace netloc sensor_data_acquisit_0_s15611_rstb 1 1 2 480J 550 NJ
+preplace netloc sensor_data_acquisit_0_s15611_sclk 1 1 2 480J 270 780J
+preplace netloc dbg_sensor_raw_data 1 1 1 490 360n
+preplace netloc dbg_sensor_data 1 1 1 470 380n
+preplace netloc dbg_sensor_valid 1 1 1 450 420n
+preplace netloc dbg_sensor_index 1 1 1 460 400n
+preplace netloc sensor_data_acquisition_data 1 1 1 530 60n
+preplace netloc axis_data_fifo_0_M_AXIS 1 2 1 NJ 90
+levelinfo -pg 1 0 240 660 800
+pagesize -pg 1 -db -bbox -sgen -190 0 950 570
+"
+}
+
   # Restore current instance
   current_bd_instance $oldCurInst
 }
@@ -483,6 +571,7 @@ proc create_hier_cell_mpsoc_ss { parentCell nameHier } {
   create_bd_pin -dir I -from 0 -to 0 dma_mm2s_intrin
   create_bd_pin -dir I -from 0 -to 0 dma_s2mm_intrin
   create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn_pl_clk0
+  create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn_pl_clk1
   create_bd_pin -dir O -from 0 -to 0 -type rst peripheral_aresetn_pl_clk3
   create_bd_pin -dir O -type clk pl_clk0
   create_bd_pin -dir O -type clk pl_clk1
@@ -492,7 +581,7 @@ proc create_hier_cell_mpsoc_ss { parentCell nameHier } {
   set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
   set_property -dict [ list \
    CONFIG.C_BAUDRATE {115200} \
-   CONFIG.C_S_AXI_ACLK_FREQ_HZ {49999500} \
+   CONFIG.C_S_AXI_ACLK_FREQ_HZ {39999599} \
  ] $axi_uartlite_0
 
   # Create instance: irq_concat, and set properties
@@ -513,6 +602,9 @@ proc create_hier_cell_mpsoc_ss { parentCell nameHier } {
   # Create instance: rst_ps8_1_49M, and set properties
   set rst_ps8_1_49M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_1_49M ]
 
+  # Create instance: rst_ps8_1_99M, and set properties
+  set rst_ps8_1_99M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_1_99M ]
+
   # Create instance: xlconstant_0, and set properties
   set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
 
@@ -1285,10 +1377,10 @@ sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#gpio0[6]#gpio0[7]#gpio0[8]#gpio0[9]#
    CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
    CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
    CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
-   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {49.999500} \
-   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {24} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {39.999599} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {30} \
    CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
-   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {50} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {40} \
    CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {RPLL} \
    CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {99.999001} \
    CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {12} \
@@ -2097,13 +2189,14 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
   connect_bd_net -net In2_1 [get_bd_pins dma_s2mm_intrin] [get_bd_pins irq_concat/In2]
   connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins irq_concat/In0]
   connect_bd_net -net clk_wiz_0_clk_300 [get_bd_pins pl_clk0] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins ps8_1_axi_periph/ACLK] [get_bd_pins ps8_1_axi_periph/M00_ACLK] [get_bd_pins ps8_1_axi_periph/M01_ACLK] [get_bd_pins ps8_1_axi_periph/M02_ACLK] [get_bd_pins ps8_1_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_1_49M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_1/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_1/pl_clk0]
+  connect_bd_net -net rst_ps8_1_299M1_peripheral_aresetn [get_bd_pins peripheral_aresetn_pl_clk1] [get_bd_pins rst_ps8_1_99M/peripheral_aresetn]
   connect_bd_net -net rst_ps8_1_299M_peripheral_aresetn [get_bd_pins peripheral_aresetn_pl_clk3] [get_bd_pins rst_ps8_1_299M/peripheral_aresetn]
   connect_bd_net -net rst_ps8_1_49M_peripheral_aresetn [get_bd_pins peripheral_aresetn_pl_clk0] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins ps8_1_axi_periph/ARESETN] [get_bd_pins ps8_1_axi_periph/M00_ARESETN] [get_bd_pins ps8_1_axi_periph/M01_ARESETN] [get_bd_pins ps8_1_axi_periph/M02_ARESETN] [get_bd_pins ps8_1_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_1_49M/peripheral_aresetn]
   connect_bd_net -net xlconcat_0_dout [get_bd_pins irq_concat/dout] [get_bd_pins zynq_ultra_ps_e_1/pl_ps_irq0]
-  connect_bd_net -net xlconstant_0_dout [get_bd_pins rst_ps8_1_299M/dcm_locked] [get_bd_pins rst_ps8_1_49M/dcm_locked] [get_bd_pins xlconstant_0/dout]
-  connect_bd_net -net zynq_ultra_ps_e_1_pl_clk1 [get_bd_pins pl_clk1] [get_bd_pins zynq_ultra_ps_e_1/pl_clk1]
+  connect_bd_net -net xlconstant_0_dout [get_bd_pins rst_ps8_1_299M/dcm_locked] [get_bd_pins rst_ps8_1_49M/dcm_locked] [get_bd_pins rst_ps8_1_99M/dcm_locked] [get_bd_pins xlconstant_0/dout]
+  connect_bd_net -net zynq_ultra_ps_e_1_pl_clk1 [get_bd_pins pl_clk1] [get_bd_pins rst_ps8_1_99M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_1/pl_clk1]
   connect_bd_net -net zynq_ultra_ps_e_1_pl_clk3 [get_bd_pins pl_clk3] [get_bd_pins rst_ps8_1_299M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_1/pl_clk3] [get_bd_pins zynq_ultra_ps_e_1/saxihpc0_fpd_aclk]
-  connect_bd_net -net zynq_ultra_ps_e_1_pl_resetn0 [get_bd_pins rst_ps8_1_299M/ext_reset_in] [get_bd_pins rst_ps8_1_49M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_1/pl_resetn0]
+  connect_bd_net -net zynq_ultra_ps_e_1_pl_resetn0 [get_bd_pins rst_ps8_1_299M/ext_reset_in] [get_bd_pins rst_ps8_1_49M/ext_reset_in] [get_bd_pins rst_ps8_1_99M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_1/pl_resetn0]
 
   # Restore current instance
   current_bd_instance $oldCurInst
@@ -2231,56 +2324,6 @@ proc create_hier_cell_dma_ss { parentCell nameHier } {
   connect_bd_net -net mpsoc_ss_pl_clk0 [get_bd_pins pl_clk0] [get_bd_pins axi_clock_converter_0/s_axi_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk]
   connect_bd_net -net sysclk_clk_wiz_clk_300mhz [get_bd_pins pl_clk3] [get_bd_pins axi_clock_converter_0/m_axi_aclk] [get_bd_pins axi_dma_0/m_axi_mm2s_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_interconnect_0/S01_ACLK] [get_bd_pins axi_interconnect_0/S02_ACLK] [get_bd_pins dma_lb_axis_switch_0/ap_clk] [get_bd_pins dma_system_ila/clk] [get_bd_pins pl_to_ps_fifo/s_axis_aclk] [get_bd_pins ps_to_pl_fifo/s_axis_aclk]
 
-  # Perform GUI Layout
-  regenerate_bd_layout -hierarchy [get_bd_cells /dma_ss] -layout_string {
-   "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"0.598824",
-   "Default View_TopLeft":"-411,3",
-   "ExpandedHierarchyInLayout":"",
-   "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
-#  -string -flagsOSRD
-preplace port DMA_S_AXI -pg 1 -lvl 0 -x -60 -y 110 -defaultsOSRD
-preplace port M00_AXI -pg 1 -lvl 4 -x 1060 -y 220 -defaultsOSRD
-preplace port SW_S_AXI -pg 1 -lvl 0 -x -60 -y 360 -defaultsOSRD
-preplace port to_pl_stream -pg 1 -lvl 4 -x 1060 -y 550 -defaultsOSRD
-preplace port to_ps_stream -pg 1 -lvl 0 -x -60 -y 660 -defaultsOSRD
-preplace port port-id_dma_mm2s_introut -pg 1 -lvl 4 -x 1060 -y 20 -defaultsOSRD
-preplace port port-id_dma_s2mm_introut -pg 1 -lvl 4 -x 1060 -y 40 -defaultsOSRD
-preplace port port-id_pl_clk0 -pg 1 -lvl 0 -x -60 -y 150 -defaultsOSRD
-preplace port port-id_pl_clk0_aresetn -pg 1 -lvl 0 -x -60 -y 230 -defaultsOSRD
-preplace port port-id_pl_clk3 -pg 1 -lvl 0 -x -60 -y 580 -defaultsOSRD
-preplace port port-id_pl_clk3_aresetn -pg 1 -lvl 0 -x -60 -y 560 -defaultsOSRD
-preplace inst axi_clock_converter_0 -pg 1 -lvl 2 -x 450 -y 400 -defaultsOSRD
-preplace inst axi_dma_0 -pg 1 -lvl 2 -x 450 -y 170 -defaultsOSRD
-preplace inst axi_interconnect_0 -pg 1 -lvl 3 -x 870 -y 220 -defaultsOSRD
-preplace inst dma_lb_axis_switch_0 -pg 1 -lvl 3 -x 870 -y 570 -defaultsOSRD
-preplace inst dma_system_ila -pg 1 -lvl 3 -x 870 -y 760 -defaultsOSRD
-preplace inst pl_to_ps_fifo -pg 1 -lvl 1 -x 100 -y 560 -defaultsOSRD
-preplace inst ps_to_pl_fifo -pg 1 -lvl 2 -x 450 -y 580 -defaultsOSRD
-preplace netloc S00_ARESETN_1 1 0 3 -30 640 260 300 680
-preplace netloc axi_dma_0_mm2s_introut 1 2 2 640J 20 NJ
-preplace netloc axi_dma_0_s2mm_introut 1 2 2 650J 40 NJ
-preplace netloc clk_300m_resetn_1 1 0 2 NJ 230 220
-preplace netloc mpsoc_ss_pl_clk0 1 0 2 NJ 150 250
-preplace netloc sysclk_clk_wiz_clk_300mhz 1 0 3 -40 650 240 30 660
-preplace netloc SW_S_AXI_1 1 0 2 NJ 360 NJ
-preplace netloc axi_clock_converter_0_M_AXI 1 2 1 670 400n
-preplace netloc axi_dma_0_M_AXIS_MM2S 1 1 2 270 40 630
-preplace netloc axi_dma_0_M_AXI_MM2S 1 2 1 N 120
-preplace netloc axi_dma_0_M_AXI_S2MM 1 2 1 N 140
-preplace netloc axi_dma_0_M_AXI_SG 1 2 1 N 100
-preplace netloc axi_interconnect_0_M00_AXI 1 3 1 NJ 220
-preplace netloc dma_lb_axis_switch_0_to_dma 1 0 4 -20 670 NJ 670 NJ 670 1040
-preplace netloc dma_lb_axis_switch_0_to_pl 1 3 1 NJ 550
-preplace netloc from_ps_stream 1 2 1 700 550n
-preplace netloc mpsoc_ss_M00_AXI 1 0 2 NJ 110 NJ
-preplace netloc to_ps_stream 1 1 2 230 500 640J
-preplace netloc to_ps_stream_1 1 0 3 NJ 660 NJ 660 690J
-levelinfo -pg 1 -60 100 450 870 1060
-pagesize -pg 1 -db -bbox -sgen -220 0 1250 970
-"
-}
-
   # Restore current instance
   current_bd_instance $oldCurInst
 }
@@ -2317,6 +2360,7 @@ pagesize -pg 1 -db -bbox -sgen -220 0 1250 970
 
   # Create ports
   set fan_pwm [ create_bd_port -dir O fan_pwm ]
+  set pl_ref_clk_25mhz [ create_bd_port -dir I -type clk -freq_hz 25000000 pl_ref_clk_25mhz ]
   set s15611_cs [ create_bd_port -dir O s15611_cs ]
   set s15611_data [ create_bd_port -dir I -from 11 -to 0 s15611_data ]
   set s15611_mclk [ create_bd_port -dir O s15611_mclk ]
@@ -2328,6 +2372,16 @@ pagesize -pg 1 -db -bbox -sgen -220 0 1250 970
   set s15611_sclk [ create_bd_port -dir O s15611_sclk ]
   set s15611_sync [ create_bd_port -dir I s15611_sync ]
 
+  # Create instance: clk_wiz_0, and set properties
+  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+  set_property -dict [ list \
+   CONFIG.CLKOUT1_JITTER {214.025} \
+   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {40} \
+   CONFIG.CLK_OUT1_PORT {clk_40mhz} \
+   CONFIG.MMCM_CLKOUT0_DIVIDE_F {30.000} \
+   CONFIG.USE_RESET {false} \
+ ] $clk_wiz_0
+
   # Create instance: dma_ss
   create_hier_cell_dma_ss [current_bd_instance .] dma_ss
 
@@ -2345,12 +2399,15 @@ pagesize -pg 1 -db -bbox -sgen -220 0 1250 970
   connect_bd_intf_net -intf_net to_ps_stream_1 [get_bd_intf_pins dma_ss/to_ps_stream] [get_bd_intf_pins sensor_ss/data]
 
   # Create port connections
-  connect_bd_net -net S00_ARESETN_1 [get_bd_pins dma_ss/pl_clk3_aresetn] [get_bd_pins mpsoc_ss/peripheral_aresetn_pl_clk3] [get_bd_pins sensor_ss/resetn]
+  connect_bd_net -net S00_ARESETN_1 [get_bd_pins dma_ss/pl_clk3_aresetn] [get_bd_pins mpsoc_ss/peripheral_aresetn_pl_clk3]
+  connect_bd_net -net clk_in1_0_1 [get_bd_ports pl_ref_clk_25mhz] [get_bd_pins clk_wiz_0/clk_in1]
+  connect_bd_net -net clk_wiz_0_clk_40mhz [get_bd_pins clk_wiz_0/clk_40mhz] [get_bd_pins sensor_ss/clk_40mhz]
+  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins sensor_ss/clk_40mhz_resetn]
   connect_bd_net -net dma_ss_dma_mm2s_introut [get_bd_pins dma_ss/dma_mm2s_introut] [get_bd_pins mpsoc_ss/dma_mm2s_intrin]
   connect_bd_net -net dma_ss_dma_s2mm_introut [get_bd_pins dma_ss/dma_s2mm_introut] [get_bd_pins mpsoc_ss/dma_s2mm_intrin]
   connect_bd_net -net mpsoc_ss_peripheral_aresetn_pl_clk0 [get_bd_pins dma_ss/pl_clk0_aresetn] [get_bd_pins mpsoc_ss/peripheral_aresetn_pl_clk0]
   connect_bd_net -net pl_clk0 [get_bd_pins dma_ss/pl_clk0] [get_bd_pins mpsoc_ss/pl_clk0]
-  connect_bd_net -net pl_clk3 [get_bd_pins dma_ss/pl_clk3] [get_bd_pins mpsoc_ss/pl_clk3] [get_bd_pins sensor_ss/master_clock]
+  connect_bd_net -net pl_clk3 [get_bd_pins dma_ss/pl_clk3] [get_bd_pins mpsoc_ss/pl_clk3] [get_bd_pins sensor_ss/clk_300mhz]
   connect_bd_net -net s15611_data_0_1 [get_bd_ports s15611_data] [get_bd_pins sensor_ss/s15611_data]
   connect_bd_net -net s15611_miso_0_1 [get_bd_ports s15611_miso] [get_bd_pins sensor_ss/s15611_miso]
   connect_bd_net -net s15611_pclk_0_1 [get_bd_ports s15611_pclk] [get_bd_pins sensor_ss/s15611_pclk]
@@ -2387,49 +2444,54 @@ pagesize -pg 1 -db -bbox -sgen -220 0 1250 970
   # Perform GUI Layout
   regenerate_bd_layout -layout_string {
    "ActiveEmotionalView":"Default View",
-   "Default View_ScaleFactor":"0.908929",
-   "Default View_TopLeft":"-197,0",
+   "Default View_ScaleFactor":"0.789655",
+   "Default View_TopLeft":"18,24",
    "ExpandedHierarchyInLayout":"",
    "guistr":"# # String gsaved with Nlview 7.0r4  2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
 #  -string -flagsOSRD
-preplace port uart_rtl -pg 1 -lvl 3 -x 880 -y 110 -defaultsOSRD
-preplace port port-id_fan_pwm -pg 1 -lvl 3 -x 880 -y 20 -defaultsOSRD
-preplace port port-id_s15611_cs -pg 1 -lvl 3 -x 880 -y 450 -defaultsOSRD
-preplace port port-id_s15611_mclk -pg 1 -lvl 3 -x 880 -y 410 -defaultsOSRD
-preplace port port-id_s15611_miso -pg 1 -lvl 0 -x 0 -y 440 -defaultsOSRD
-preplace port port-id_s15611_mosi -pg 1 -lvl 3 -x 880 -y 470 -defaultsOSRD
-preplace port port-id_s15611_mst -pg 1 -lvl 3 -x 880 -y 430 -defaultsOSRD
-preplace port port-id_s15611_pclk -pg 1 -lvl 0 -x 0 -y 480 -defaultsOSRD
-preplace port port-id_s15611_rstb -pg 1 -lvl 3 -x 880 -y 510 -defaultsOSRD
-preplace port port-id_s15611_sclk -pg 1 -lvl 3 -x 880 -y 490 -defaultsOSRD
-preplace port port-id_s15611_sync -pg 1 -lvl 0 -x 0 -y 460 -defaultsOSRD
-preplace portBus s15611_data -pg 1 -lvl 0 -x 0 -y 500 -defaultsOSRD
-preplace inst dma_ss -pg 1 -lvl 1 -x 230 -y 150 -defaultsOSRD
-preplace inst mpsoc_ss -pg 1 -lvl 2 -x 610 -y 140 -defaultsOSRD
-preplace inst sensor_ss -pg 1 -lvl 2 -x 610 -y 450 -defaultsOSRD
-preplace netloc S00_ARESETN_1 1 0 3 70 300 390 330 860
-preplace netloc dma_ss_dma_mm2s_introut 1 1 1 390 140n
-preplace netloc dma_ss_dma_s2mm_introut 1 1 1 400 160n
-preplace netloc mpsoc_ss_peripheral_aresetn_pl_clk0 1 0 3 50 280 NJ 280 850
-preplace netloc pl_clk0 1 0 3 40 270 NJ 270 820
-preplace netloc pl_clk3 1 0 3 60 290 400 320 830
-preplace netloc sensor_data_acquisit_0_s15611_cs 1 2 1 NJ 450
-preplace netloc s15611_data_0_1 1 0 2 NJ 500 NJ
-preplace netloc sensor_data_acquisit_0_s15611_mclk 1 2 1 NJ 410
-preplace netloc s15611_miso_0_1 1 0 2 NJ 440 NJ
+preplace port uart_rtl -pg 1 -lvl 3 -x 1090 -y 110 -defaultsOSRD
+preplace port port-id_fan_pwm -pg 1 -lvl 3 -x 1090 -y 20 -defaultsOSRD
+preplace port port-id_pl_ref_clk_25mhz -pg 1 -lvl 0 -x 0 -y 400 -defaultsOSRD
+preplace port port-id_s15611_cs -pg 1 -lvl 3 -x 1090 -y 430 -defaultsOSRD
+preplace port port-id_s15611_mclk -pg 1 -lvl 3 -x 1090 -y 450 -defaultsOSRD
+preplace port port-id_s15611_miso -pg 1 -lvl 0 -x 0 -y 490 -defaultsOSRD
+preplace port port-id_s15611_mosi -pg 1 -lvl 3 -x 1090 -y 470 -defaultsOSRD
+preplace port port-id_s15611_mst -pg 1 -lvl 3 -x 1090 -y 490 -defaultsOSRD
+preplace port port-id_s15611_pclk -pg 1 -lvl 0 -x 0 -y 510 -defaultsOSRD
+preplace port port-id_s15611_rstb -pg 1 -lvl 3 -x 1090 -y 510 -defaultsOSRD
+preplace port port-id_s15611_sclk -pg 1 -lvl 3 -x 1090 -y 530 -defaultsOSRD
+preplace port port-id_s15611_sync -pg 1 -lvl 0 -x 0 -y 530 -defaultsOSRD
+preplace portBus s15611_data -pg 1 -lvl 0 -x 0 -y 470 -defaultsOSRD
+preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 430 -y 400 -defaultsOSRD
+preplace inst dma_ss -pg 1 -lvl 1 -x 430 -y 160 -defaultsOSRD
+preplace inst mpsoc_ss -pg 1 -lvl 2 -x 820 -y 150 -defaultsOSRD
+preplace inst sensor_ss -pg 1 -lvl 2 -x 820 -y 470 -defaultsOSRD
+preplace netloc S00_ARESETN_1 1 0 3 60 290 NJ 290 1050
+preplace netloc clk_in1_0_1 1 0 1 N 400
+preplace netloc clk_wiz_0_clk_40mhz 1 1 1 600 390n
+preplace netloc clk_wiz_0_locked 1 1 1 590 410n
+preplace netloc dma_ss_dma_mm2s_introut 1 1 1 590 150n
+preplace netloc dma_ss_dma_s2mm_introut 1 1 1 610 170n
+preplace netloc mpsoc_ss_peripheral_aresetn_pl_clk0 1 0 3 50 280 N 280 1060
+preplace netloc pl_clk0 1 0 3 30 300 N 300 1040
+preplace netloc pl_clk3 1 0 3 40 310 610 310 1030
+preplace netloc s15611_data_0_1 1 0 2 NJ 470 NJ
+preplace netloc s15611_miso_0_1 1 0 2 NJ 490 NJ
+preplace netloc s15611_pclk_0_1 1 0 2 NJ 510 NJ
+preplace netloc s15611_sync_0_1 1 0 2 NJ 530 NJ
+preplace netloc sensor_data_acquisit_0_s15611_cs 1 2 1 NJ 430
+preplace netloc sensor_data_acquisit_0_s15611_mclk 1 2 1 NJ 450
 preplace netloc sensor_data_acquisit_0_s15611_mosi 1 2 1 NJ 470
-preplace netloc sensor_data_acquisit_0_s15611_mst 1 2 1 NJ 430
-preplace netloc s15611_pclk_0_1 1 0 2 NJ 480 NJ
+preplace netloc sensor_data_acquisit_0_s15611_mst 1 2 1 NJ 490
 preplace netloc sensor_data_acquisit_0_s15611_rstb 1 2 1 NJ 510
-preplace netloc sensor_data_acquisit_0_s15611_sclk 1 2 1 NJ 490
-preplace netloc s15611_sync_0_1 1 0 2 NJ 460 NJ
-preplace netloc S_AXI_LITE_1 1 0 3 20 10 NJ 10 860
+preplace netloc sensor_data_acquisit_0_s15611_sclk 1 2 1 NJ 530
+preplace netloc S_AXI_LITE_1 1 0 3 20 0 NJ 0 1060
 preplace netloc axi_uartlite_0_UART 1 2 1 NJ 110
-preplace netloc dma_ss_M00_AXI 1 1 1 N 120
-preplace netloc mpsoc_ss_M02_AXI 1 0 3 30 260 NJ 260 840
-preplace netloc to_ps_stream_1 1 0 3 20 310 NJ 310 840
-levelinfo -pg 1 0 230 610 880
-pagesize -pg 1 -db -bbox -sgen -190 0 1030 560
+preplace netloc dma_ss_M00_AXI 1 1 1 N 130
+preplace netloc mpsoc_ss_M02_AXI 1 0 3 60 10 NJ 10 1030
+preplace netloc to_ps_stream_1 1 0 3 20 320 NJ 320 1030
+levelinfo -pg 1 0 430 820 1090
+pagesize -pg 1 -db -bbox -sgen -190 -10 1240 580
 "
 }
 
diff --git a/xdc/top.xdc b/xdc/top.xdc
index 5bdc3a1710623c5fe8fa0ea9756e2a5bcd0c717d..fda23e5be9ad8ac6283d0db40b8b55804dd64855 100644
--- a/xdc/top.xdc
+++ b/xdc/top.xdc
@@ -1,3 +1,8 @@
+# PL_REF_CLK_25MHZ_1V8
+set_property PACKAGE_PIN M6 [get_ports pl_ref_clk_25mhz]
+set_property IOSTANDARD LVCMOS18 [get_ports pl_ref_clk_25mhz]
+create_clock -period 40 -name pl_ref_clk_25mhz -waveform {0 20} [get_ports pl_ref_clk_25mhz]
+
 # UART
 set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_txd]
 set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_rxd]
@@ -51,3 +56,9 @@ set_property PACKAGE_PIN E14 [get_ports {s15611_data[10]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {s15611_data[10]}]
 set_property PACKAGE_PIN E13 [get_ports {s15611_data[11]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {s15611_data[11]}]
+
+create_clock -period 25 -name s15611_pclk -waveform {0 12.5} [get_ports s15611_pclk]
+set_input_delay -clock s15611_pclk -min 0 [get_ports {s15611_data[*]}]
+set_input_delay -clock s15611_pclk -max 3 [get_ports {s15611_data[*]}]
+set_input_delay -clock s15611_pclk -min 0 [get_ports s15611_sync]
+set_input_delay -clock s15611_pclk -max 3 [get_ports s15611_sync]
\ No newline at end of file